Solid Mobile Phone: Toshiba Proclaims FeRAM Breakthrough

Toshiba Corp. this week announced the prototype of a new FeRAM
(ferroelectric random access memory), which, according to the company,
redefines industry benchmarks for density and operating speed. The new
chip realizes storage of 128Mb (16MB) and read and write speeds of
1.6GB/s, the most advanced combination of performance and density yet
achieved.

FeRAM combines the relatively fast operating characteristics of DRAM
with flash memory's ability to retain data while powered off,
attributes that continue to attract the attention of the semiconductor
industry. No commercial devices are available, but many companies
explore the technology rather rigorously.

The new FeRAM modifies Toshiba's original chainFeRAM architecture,
which significantly contributes to chip scaling, with a new
architecture that prevents cell signal degradation, the usual tradeoff
from chip scaling. The combination realizes an upscaled FeRAM with a
density of 128Mb. Furthermore, a new circuit that predicts and
controls the fluctuations of power supply supports high-speed data
transfers. This allowed integration of DDR2 interface to maximize data
transfers at a high throughput at low power consumption, realizing
read and write speeds of 1.6GB/s. In developing the new FeRAM, Toshiba
broke its own record of 32Mb density and 200Mb data transfers, pushing
performance to eight times faster than the transfer rate and density
of the previous records and the fastest speed of any non-volatile RAM.

ChainFeRAM in the earlier generation of 64-megabit FeRAM employed a
data-line design in which neighboring data-lines operated in sequence:
one is off when the other is on. This allowed off lines to provide a
noise barrier between on lines, contributing to chip scaling and fine
performance. Previous chain architecture collected four data-lines but
Toshiba has successfully increased the number of data-lines to eight,
which led to a decrease in the total chip area.